Various switching circuits have been devised for a number of years to achieve the purpose of high speed switching.
For example, emitter-coupled logic (ECL) switching circuits comprise a pair of differential bipolar transistors. the emitters of the two transistors are joined together and are biased by a constant current source which is usually implemented with a transistor circuit. The bases of the differential pair of transistors receive, and are controlled by, differential inputs signals.
Although ECL circuits can operate at very high speed, they use bipolar transistor technology, which is more expensive to implement than the metal-oxide semiconductor (MOS) technology used in many digital integrated circuits. In addition, bipolar circuits dissipate more power than MOS circuits do.
Recently, some MOS switching circuits comprising a source-coupled transistor pair have been published which are similar to the ECL switching circuits.
When a source-coupled MOS transistor pair is used as a differential switch, the current conversion speed is limited by the switching time of the differential switch. Turning the switching MOS transistors on or off requires currents to flow into or out of the internal parasitic capacitances in both transistors, so that it takes more time to perform the switching operation than with an ECL switch. Hence the voltage fluctuation across the parasitic capacitances in both MOS transistors must be kept as small as possible.
In U.S. Pat. No. 4,721,866, Chi et al. disclose that two buffers be used for limiting the voltage swings, to ensure that the switching transistors are not both in the off state at the same time. Each buffer further includes a load transistor to reduce the voltage swing of the control signals. The load transistor is connected as a diode. According to this implementation, the voltage of the control signal can be reduced only by the threshold voltage V.sub.th of the load transistor. It is quite difficult to obtain the optimum operating point to acquire the minimum fluctuation in both transistors with such a switching circuit.
It is an object of this invention to provide a CMOS current steering switching circuit that can decrease the switching response time to the differential input control signals.
The circuit diagram of a current steering switch with a constant current source is shown in FIG. 1. Two p-channel transistors constitute a source-coupled differential pair, to the source coupling node of which a constant current source is connected. The drain terminals of the source-coupled transistors comprise the output terminals of the switching circuit. The current source is switched toward one of the two output lines depending on the control signals received by the gate terminals of the differential pair. The current source comprises two p-channel transistors connected in series, the gate terminals of which are biased by two selected voltages to provide a constant current.
For exact operation of the circuit, it is necessary to avoid simultaneous turn-off of the differential switching transistors. This is because if both switch transistors are off, the output node of the current source is rapidly discharged so that the current source comes into the nonsaturation region of operation. The following recharging slows the operation of the circuit. In other words, the voltage fluctuation range of the source coupling node of the differential pair must be kept as small as possible to achieve fast response.
According to the phenomenon mentioned above, the gate signals which control the switch transistor pair should be carefully designed to ensure that the switch transistors are not both off.